Wafer-to-wafer bonding for hermetic and vacuum packaging of smart sensors

Abstract

In this presentation, we will review recent advances in the development of low temperature wafer-to-wafer bonding for the fabrication of hermetic and/or vacuum enclosures for sensors that are monolithically integrated with supporting electronic circuitry. The presence of CMOS circuitry with its limited thermal budget and the requirement of low pressures inside the microchamber impose strict requirements on the bonding process. We will describe metal-based approaches that leverage mature deposition and patterning techniques developed for integrated circuits (ICs) and micro-electro-mechanical systems (MEMS). The ability to produce finely patterned metal seals significantly reduces the real estate required for bonding and therefore lowers the size, weight, and cost of the device. In addition, massively parallel wafer-level processing drastically reduces the cost of the device. Metal-based approaches can be executed at low temperatures compatible with CMOS circuits and can be integrated with various substrate materials and topographies, making them ideal for smart sensors such as microbolometer FPAs.