Wafer-level 3-D integration moving forward

Abstract

Three-dimensional integration represents a system-level integration scheme wherein multiple layers of planar devices are stacked and interconnected using through-silicon vias in the Z direction.¹ Conceptually, 3-D can alleviate interconnect delay problems, while reducing chip area. If a large number of the long interconnects needed in two-dimensional structures can be replaced by a short vertical interconnect, this would greatly enhance the performance of logic circuits. For instance, logic gates on a critical path can be placed very close to each other by positioning them on multiple active layers. Circuits with different voltage requirements and/or performance requirements can also be put on different layers.