ROIC for 3 μm pixel pitch colloidal quantum dot detectors

Abstract

The DARPA Wafer-scale Infrared Detectors (WIRED) program requires the development of low cost detector technologies with high quantum efficiency and low dark current based on colloidal quantum dots (CQDs) of compound semiconductors. The program targets the SWIR (900 – 1700 nm) spectral range. This paper focuses on the design of 3 μm pitch, low noise ROICs for interfacing with SWIR CQD detectors. So far, the team has developed and demonstrated PV detector technology based on thin film CQDs IR-absorbing materials. The CQD films are deposited by spin-coating from solution directly on ROIC and fanout wafers at room temperature. The photodiode fabrication is fully compatible with CMOS fabrication at the wafer-level, allowing for large format FPAs limited only by the ROIC size. This paper outlines the preliminary design of a 3 μm pitch 1920 x 1080 modular ROIC, easily scalable to larger formats by mask stitching.
DRS has designed a full HD (1920x1080) readout integrated circuit (ROIC) specifically for cost-effective waferscale infrared (WIRED) detectors on 3 μm pitch, for best theoretical image quality optical system performance. The sensor’s pixels use a capacitive trans-impedance amplifier (CTIA) and a metal-insulator-metal (MIM) integration capacitor, to achieve 22 Ke- well capacity, 0.7 V output swing and 37 e- or 18 e- equivalent readout noise, operating at 60 Hz ripple readout mode or 30 Hz correlated double sampling (CDS) mode, respectively. The fully digital ROIC consumes approximately 0.5 W of power, allowing it to be fielded in battery-powered applications.