RTI uses cookies to offer you the best experience online. By clicking “accept” on this website, you opt in and you agree to the use of cookies. If you would like to know more about how RTI uses cookies and how to manage them please view our Privacy Policy here. You can “opt out” or change your mind by visiting: http://optout.aboutads.info/. Click “accept” to agree.
InAlN/GaN heterostructure field-effect transistors (HFETs) have been grown and fabricated on Fe-doped semi-insulating c-plane GaN substrates. The problematic parasitic leakage caused by interface charge between the epitaxial layers and the GaN substrate as well as any adverse effect of the substrate surface damage caused by the mechanical chemical polish employed on the substrates has been circumvented by using a combination of inductively coupled plasma dry etching and in situ H(2) etching. As a result, the current leakage for 100 mu m separation mesa-to-mesa was reduced down to 3x10(-9) A/mm at 10 V voltage bias for a 320 mu m mesa pad width normal to the current flow direction and the corresponding GaN buffer resistivity was about 3.5x10(8) Omega cm. Owing to the good thermal conductivity of GaN substrates, the HFETs exhibit much less current degradation, compared to those on a sapphire substrate, at high drain biases. Likewise, the dc and pulsed I-V characteristics were reasonably similar, suggestive of negligible drain current lag. A dc saturation drain current density of 1.0 A/mm was achieved at zero gate bias. For HFETs with 1.1 mu m gate length and 90 mu m gate width, the maximum extrinsic dc transconductance was 275 mS/mm. (C) 2010 American Vacuum Society. [DOI: 10.1116/1.3481138]
