RTI uses cookies to offer you the best experience online. By clicking “accept” on this website, you opt in and you agree to the use of cookies. If you would like to know more about how RTI uses cookies and how to manage them please view our Privacy Policy here. You can “opt out” or change your mind by visiting: http://optout.aboutads.info/. Click “accept” to agree.
3-D integration technology for high performance detector arrays
Temple, D., Bower, C., Malta, D., Robinson, JE., Coffman, PR., Skokan, MR., Welch, TB., Garrou, P. (Ed.), Ramm, P. (Ed.), & Takahashi, K. (Ed.) (2006). 3-D integration technology for high performance detector arrays. MRS Proceedings, 970, 0970-Y03-04. https://doi.org/10.1557/PROC-0970-Y03-04
This paper describes a technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of detector devices hybridized with Si electronics. The focus of the paper is on high performance infrared focal plane arrays based on HgCdTe, which offer the ultimate in infrared sensitivity and find application in high performance military systems. Performance data from test FPA devices with integrated multilayer Si stacks are discussed in this paper.
