Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics (invited paper)

Dean M. Malta; Dorota S. Temple; Erik P. Vick; Matthew R. Lueck; Dorota S. Temple; Erik P. Vick; Matthew R. Lueck; Dean M. Malta; M Skokan; Christopher Masterjohn; Mark Muzilla

Enabling more capability within smaller pixels

advanced wafer-level process technologies for integration of focal plane arrays with readout electronics (invited paper)

Temple, D., Vick, E., Lueck, M., Malta, D., Skokan, M., Masterjohn, C., & Muzilla, M. (2014). Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics (invited paper). Proceedings of SPIE, 9100, 91000L1 - 9100L7. https://doi.org/10.1117/12.2054106

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Abstract

Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.