RTI International to hold 3D Architectures for Semiconductor Integration and Packaging Conference

RESEARCH TRIANGLE PARK, NC – The upcoming 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference will provide an opportunity for leaders from around the world to come together to discuss industry efforts and technology surrounding 2.5/3D device and systems integration and packaging. 

The 2014 3D ASIP Conference, coordinated by RTI International, will be held Dec. 10-12 at the Hyatt Regency San Francisco Airport Hotel in Burlingame, California. 

The conference will look at the entire eco-system, from design through manufacturing to market applications.

Since the conference series started more than a decade ago, 2.5D/3D technology and its market forecast have evolved significantly. Experts today often disagree about the implications and timeframe of bringing the technology to large-scale commercial adoption. Participants at this year's conference will learn the latest perspectives, and how best to position their efforts to meet the industry opportunity. 

RTI will also host a preconference symposium titled "3D Integration: 3D Process Technology" on Dec. 10, organized and moderated by Phil Garrou, IEEE fellow and consultant. 

Dean Malta, engineering manager of 3D integration at RTI will deliver a presentation called "TSV Formation: Drilling and Filling, and John Lannon, director of Microsystem Integration and Packaging at RTI, will give a presentation called "Si Interposers- Making the Move from PWB to Si."

Additionally, 3D processes are covered in detail in the recent Handbook of 3D Integration: Volume 3 - 3D Process Technology, which includes chapters by RTI researchers, and is edited by Garrou. 

For more information on the 2014 3D Architectures for Semiconductor Integration and Packaging Conference, including registration, sponsorship and exhibiting details, visit www.3dasip.org.